Drive control system

ABSTRACT

A drive control system having constituent devices such as control unit for drive control, servo amplifier for driving motor by receiving a command from the control unit, spindle amplifier, and input and output unit, with these constituent devices connected so as to communicate with each other, in which a memory is provided in each constituent device, the constituent devices are synchronized with each other, a communication unit is provided for transferring memory data between arbitrary constituent devices, and the memory is shared between arbitrary constituent devices.

TECHNICAL FIELD

The present invention relates to a drive control system. Moreparticularly this invention relates to a drive control system fordriving and controlling the plurality of servo motors or spindle motorsin machine tools and industrial machines.

BACKGROUND ART

Drive control systems for driving and controlling the plurality of servomotors or spindle motors in machine tools and industrial machines aredisclosed, for example, in Japanese Patent Application Laid-Open No.3-245204 and Japanese Patent Application Laid-Open No. 4-290102.

FIG. 16 shows an outline of a prior art drive control system asdisclosed in the above patent publications. This drive control systemcomprises one control unit 500, a plurality of servo amplifiers orspindle amplifiers (hereinafter called servo amplifiers) 510, and aplurality of remote input and output (remote IO) units 520, and thecontrol unit (master) 500 is the host device, to which servo amplifiers(slaves) 510 with CPU and remote IO units 520 are connected withcommunication lines 600, 601 in two-way communication manner.

The control unit 500 includes the CPU (M/CPU) 501, a serialcommunication interface for servo amplifier 502, and a serialcommunication interface for IO unit 503. The serial communicationinterface for servo amplifier 502 and serial communication interface forIO unit 503 respectively incorporates transmission memories 502 a, 503a, and reception memories 502 b, 503 b.

The servo amplifier 510 individually has a CPU (S/CPU) 511, a motordrive circuit (M/D) 512, and a serial interface 513 for communicationwith the control unit 500, and a servo motor 530 is connected thereto.The serial communication interface 513 is same as the serialcommunication interface such as serial communication interface 502, andincludes a transmission memory 513 a and a reception memory 513 b.

The CPU 501 of the control unit 500 transmits command data or parameterto the servo amplifier 510 through the serial communication interface502 by serial transmission, and the CPU 511 of the servo amplifier 510receives the transmitted command data or parameter through the serialcommunication interface 513, and drives and controls the servo motor 530by using the motor drive circuit 512.

The remote IO unit 520 includes a digital input interface (DI) 521, adigital output interface (DO) 522, and a serial communication interface523 for communication with the control unit 500. The serialcommunication interface 523 is a same serial communication interface asthe serial communication interface 503, and includes a transmissionmemory 523 a and a reception memory 523 b.

The remote IO unit 520 transmits data of the state of DI interface 521to the control unit 500 through the serial communication interface 523,and the control unit 500 receives the transmitted digital output datathrough the serial communication interface 523, and produces digitaloutput from the DO interface 522.

FIG. 17 shows a prior art of serial communication interface used in suchdrive control system. A transmission memory 700 and a reception memory701 are composed of dual port RAMs, and are connected to an externaladdress bus 702 and an external data bus 703 at one side. A CPU 501(511) writes transmission data from an external bus interface 704 intothe transmission memory 700.

Transmission function in the serial communication interface begins bystarting up a transmission-reception controller 706 by a transmissionstart signal from a synchronous clock generator 705. Thetransmission-reception controller 706 writes the transmission addressset value and transmission data length set value being set in atransmission-reception control register setting unit 707 into atransmission address counter 708, and transmits the sequentiallycounted-up transmission address to an address decoder 709, so that thedata in the transmission memory 700 is sent into a transmission register710 to be transmitted. In a redundancy code generator 711, from similartransmission data, a redundancy code is generated, and after sending outthe final transmission data, the redundancy code is sent into thetransmission register 710 to be transmitted.

Reception function begins when the data received in a reception register712 is transferred to a start flag detector 713, and thetransmission-reception controller 706 is started by a start signalgenerated by detection of start flag in reception data. Thetransmission-reception controller 706 writes the reception address setvalue in the transmission-reception control register setting unit 707into a reception address counter 714, and counts up at every datareception. By transmitting the counted-up reception address to theaddress decoder 709, reception data is written into the reception memory701.

A communication failure detector 715 compares the redundancy code addedto the end of the reception data and the redundancy code generated fromthe reception data, and detects if the communication is finishednormally. The result of detection is written in the communicationabnormality status in the transmission-reception control registersetting unit 707. The CPU 501 (511) reads this communication abnormalitystatus, and uses for control if normal, and discards the reception dataif abnormal.

FIG. 18 shows communication timing in the conventional drive controlsystem, and FIG. 19 shows outline of communication data. In FIG. 19, (a)shows communication data to be transmitted from the control unit 500 tothe servo amplifier 510, (b) shows communication data to be transmittedfrom the servo amplifier 510 to the control unit 500, (c) showscommunication data to be transmitted from the control unit 500 to theremote IO unit 520, and (d) shows communication data to be transmittedfrom the remote IO unit 520 to the control unit 500.

The control unit 500 transmits data simultaneously to the servoamplifier 510 and remote IO unit 520 in synchronism with the clock T1.As shown in FIG. 19(a) and FIG. 19(c), a synchronous code is included inthe data transmitted from the control unit 500 to the servo amplifier510, and in the data transmitted to the remote IO unit 520, and theservo amplifier 510 and remote IO unit 520 detect the synchronous codefrom the reception data, and generate a clock synchronized with clock T1in the control unit 500.

The servo amplifier 510 divides this clock, and transmits the data shownin FIG. 19(b) to the control unit 500 at the predetermined timingindicated by codes S1 to S5 in FIG. 18. The remote IO unit 520 alsotransmits the data shown in FIG. 19(d) to the control unit 500 at thepredetermined timing indicated by codes R1 to R7 in FIG. 18.

The command data transmitted from the control unit 500 to the servoamplifier 510 is entirely transmitted to the servo amplifier 510, andthe feedback data taken in by the servo amplifier 510 is individuallytransferred from each servo amplifier 510 to the control unit 500, andis managed totally in the control unit 500. Similarly, the input data ofthe remote IO unit 520 is transferred to the control unit 500, and ismanaged totally in the control unit 500.

Data TS1, TS2 to TSn, RS1, RS2 to RSn in the transmission memory 502 aand reception memory 502 b for servo amplifiers in the control unit 500shown in FIG. 16 show the sharing relation of transmission and receptiondata, and the control unit 500 totally manages the transmission andreception data of all servo amplifiers 510. By contrast, the datamanaged in each servo amplifier 510 is the own individual data, and itis known the data managed in each servo amplifier 510 is different. DataDO1, DO2 to DOn, DI1, DI2 to DIn in the transmission memory 503 a andreception memory 503 b for remote IO unit of the control unit 500 showthe sharing relation of transmission and reception data, and the controlunit 500 totally manages the transmission and reception data of allremote IO units 520, but the transmission and reception data managed ineach remote IO unit 520 is also different in each unit.

In this conventional drive control system, the transmission andreception data of the servo amplifiers 510 and remote IO units 520 aretotally managed in the control unit 500, but the data managed in eachservo amplifier 510 is the own individual data, and mutual feedbackstate is not known among servo amplifiers 510.

Besides, since the communication system is separated between the remoteIO units 520 and servo amplifiers 510, the state of the remote IO units520 cannot be read directly from the servo amplifiers 510, or feedbackdata cannot be sent out.

In the conventional drive control system, meanwhile, since thetransmission timing is managed in time division as shown in FIG. 18, ifthe quantity of data to be transferred is small, an idle time occurs inthe transmission route, and the communication efficiency is poor, or thequantity of data exceeding the assigned transmission time cannot betransferred. Still more, the transmission timing is limited by thenumber of time divisions due to the number of axes to be connected, andsince the transmission timing is divided in time, the transmissiontiming cannot be changed, and a communication line must be newlyextended in order to add the servo amplifiers by more than the number ofpredetermined time divisions.

In the drive control system, the communication system for remote IO unitis required to respond to the input and output function at high speed,and therefore, in the prior art, it was necessary to transmit andreceive data for the total number of input and output points of allremote IO units connected in every period regardless of the transmissionin a constant period and changes of input and output states. As aresult, data is exchanged more than necessary, the total number ofremote IO units is limited to a smaller number, and the communicationperiod (communication period T1 in FIG. 18) becomes long, therebydeteriorating the response.

In the transmission data, high speed data necessary for motor controland low speed data such as parameter coexist, and the quantity ofcommunication data increases, and the communication time per data isextended, and hence the number of time divisions is limited.

Further, to read the state between servo amplifiers 510, it is requiredto transmit data twice through the control unit, and delay time occurs,and the performance of the entire drive control system is lowered.Moreover, the CPU 501 of the control unit 500 requires processing oftransfer program, and the load of the CPU 501 increases.

As shown in FIG. 20(a), when the servo amplifier 510 requests output toa certain remote IO unit 520 through the communication system, itrequires a series of processes including preparation of request data ofDO output in the servo amplifier, transmission of request data,reception processing and preparation of request data of DO output in themaster (control unit), transmission of request data of DO output, andreception processing in remote IO unit, and delay time of about 3 timesof communication period T1 occurs, and the response is poor.

Similarly, receiving the input of the remote IO unit 520, to start themotor actually by the servo amplifier 510, as shown in FIG. 20(b), itrequires a series of processes including transmission of DI data in theIO unit 520, reception processing and start signal processing in themaster (control unit), data transmission, and start signal reception inthe servo amplifier 510, the IO unit 520 input DI (start signal) anddelay time of about 4 times of communication period T1 occurs, and theresponse is poor.

Other prior art of drive control system includes a drive control systemfor multiple axes for sharing part or all of input data by a pluralityof servo amplifiers without using host control unit, and issuing outputsignals from each servo amplifier.

This drive control system is explained by referring to FIG. 21 to FIG.24. FIG. 22 to FIG. 24 show one drive control system, which is dividedinto three drawings in order to avoid complicated expression of wiring.

There are three servo amplifiers 800 for first axis, second axis, andthird axis, and they are composed identically, each comprising a CPU801, a motor drive circuit 802, a digital input interface 803, a digitaloutput interface 804, an analog input interface (A/D) converter 805 forspeed command, and a pulse train input interface 806 for positioncommand, and a servo motor 810 with a rotary encoder is connected toeach servo amplifier 800.

As shown in FIG. 21(a), (b), (c), input signals of functions 1 to 8 areassigned in the digital input interface 803 of the servo amplifiers 800for all of first to third axes, output signals of functions 11 to 18 areassigned in the digital output interface 804 for first axis, outputsignals of functions 21 to 24 for second axis, and output data offunctions 31 and 32 for third axis.

When the input and output signals are assigned in the input and outputinterfaces of servo amplifiers 800 in this manner, the wiring of theinput and output signals becomes as shown in FIG. 22. As shown in FIG.22, input signals of functions 1 to 8 are branched in three terminals ina relay terminal block 820, and wired to servo amplifiers 800 for firstto third axes, and many wires are needed. Output signals for functions11 to 18, functions 21 to 24, and functions 31 and 32 are also wiredfrom the servo amplifiers 800 to the relay terminal block 820.

In the servo amplifier 800 for first axis, since output signals forfunctions 11 to 18 are used, there is no vacancy in the digital outputinterface 804, but in the servo amplifiers 800 for second axis and thirdaxis, there is a vacancy in the digital output interfaces 804. However,as the output function, if desired to add an output signal for function19 to the servo amplifier 800 for first axis, there is no extra room foraddition. Similarly, as input function, input signal for function 9cannot be added.

Thus, in the conventional drive control system, multiple wires areconnected to the servo amplifiers 800, and the wiring include manyconnections, and wiring and maintenance works are complicated. It isalso difficult to add input and output functions, and input and outputinterfaces having extra input and output points may be prepared in theservo amplifiers 800.

As shown in FIG. 23, in the wiring of analog speed command signals, eachone of the servo amplifiers 800 for first axis to third axis requireswiring of analog speed command signals, and a speed command unit 830requires analog output interfaces 831 for several axes, and similarwiring is required if operating the servo amplifier 800 of each axis bythe same analog speed command. In the wiring shown in FIG. 23, if thefirst axis to third axis are synchronously controlled by the samecommand, in case synchronous control fails due to some trouble,fluctuations cannot be controlled in each axis, and synchronism maydeviated.

As shown in FIG. 24, in the wiring of pulse train position commandsignals, each one of the servo amplifiers 800 for first axis to thirdaxis requires wiring of pulse strain command signals, and a positioncommand unit 840 requires pulse generators 841 for several axes, andsimilar wiring is required if operating by the same position command.

The invention is devised to solve these problems, and it is hence anobject thereof to present a drive control system capable of driving andcontrolling with an excellent response without increasing the load ofCPU of the host control unit, and moreover excellent in transmissionefficiency, and capable of decreasing the communication data quantity ofhigh speed synchronous communication, determining the data length freelyregardless of the divided time, and curtailing the number of wiringconnections, and further flexible in addition of input and outputfunctions, and capable of realizing advanced synchronous operation andarbitrary synchronous operation without causing deviation insynchronism.

DISCLOSURE OF THE INVENTION

To achieve the object, the invention presents a drive control systemhaving constituent devices such as control unit, servo amplifier,spindle amplifier, and input and output unit, with these constituentdevices connected so as to communicate with each other, in which amemory is provided in each constituent device, the constituent devicesare synchronized with each other, communication unit is provided fortransferring memory data between arbitrary constituent devices, and thememory is shared between arbitrary constituent devices.

Therefore, since the memory can be shared in the drive control system,batch management of memories of control unit is not necessary, and theload of the control unit CPU is not increased, and time delay does notoccur, the feedback state is mutually known among servo amplifiers, andthe output request can be directly sent from the servo amplifier to theinput and output unit, and the input state can be read immediately.

In the drive control system of the invention, the communication data iscomposed of a synchronous packet used for generating a clock transmittedin a specific period so that all constituent devices are synchronizedtherewith, an in-channel communication packet used for sharing thememory within a same group, an allout communication packet used forsharing the memory by all constituent devices, and a designateddestination communication packet for communicating by designating thedestination of transmission of parameter, etc.

Therefore, the idle time of transmission route is shortened and thetransmission efficiency is enhanced, and the data requiring high speedsynchronous communication is changed into a synchronous packet and anin-channel communication packet, while the low speed data is changed toa designated destination transmission, and hence the communication dataquantity of high speed synchronous communication is decreased, and thenumber of axes to be connected is increased. At the same time, the datalength can be determined arbitrarily regardless of the divided time.

In the drive control system of the invention, further, the control unitand servo amplifier has a communication memory in each channel, atransmitter transmits the in-channel communication packet includingchannel designated value, address, transmission data length and data toall constituent devices, and a receiver judges approval or rejection ofreception by collating the channel designated value included in thecommunication packet and the channel set value set in the parameter ineach servo amplifier, and writes the data of the communication packet ofthe collated channel in the communication memory in the memory.

Therefore, the communication in the channel is made in the sameprocedure as the allout communication, and the size of the memory can beset in an appropriate capacity in each channel.

Also in the drive control system of the invention, the control unit,servo amplifier and input and output unit have allout communicationmemories, a transmitter transmits an allout communication packetincluding the sender number, address, transmission data length, variabledata length, previous data, and rewrite data to all constituent devices,and a receiver compares the received previous data and the data in thepresent allout communication memory, rewrites the data in the alloutcommunication memory if matched, and stops writing into the alloutcommunication memory if not matched.

Therefore, since the data can be transmitted by designating the addressand data length, the memory common to the constituent devices of thedrive control system can be managed, and instead of communicating dataof all input points in all input and output units in every specificperiod as in the prior art, only the changed input and output data arecommunicated, so that the efficiency of transmission route is enhanced.

Also in the drive control system of the invention, a transmitter adds aredundancy code to the communication packet in every quantity of datasuited to the size of the buffer of transmission and reception, and areceiver detects communication failure according to the redundancy codein every quantity of data suited to the size of the buffer oftransmission and reception, and stops writing into the memory ifabnormal.

Therefore, by adding the plurality of redundancy codes in thecommunication data, data exceeding the reception buffer can be received,and if communication failure occurs in the received data, breakdown ofshared memory can be prevented.

Also in the drive control system of the invention, the waiting time ofeach communication following the synchronous packet is shorteneddepending on the priority order, and when a constituent device high inpriority order starts transmission within waiting time, reception isstarted, and after completion of reception if other constituent devicedoes not start transmission after lapse of a specified waiting time,transmission is started.

Therefore, the idle time of transmission route is shortened and thetransmission efficiency is enhanced, and the data requiring high speedsynchronous communication is changed into a synchronous packet and anin-channel communication packet, while the low speed data is changed toa designated destination transmission, and hence the communication dataquantity of high speed synchronous communication is decreased, and thenumber of axes to be connected is increased.

Also in the drive control system of the invention, the memory storingthe input data, output data, position command, and speed command isshared by the constituent devices.

Therefore, it is not necessary to connect wiring of signal lines ofinput data, output data, position command, and speed command repeatedlyin every constituent device.

Also in the drive control system of the invention, the present positiondata of each axis is shared by the synchronous axis, and it iscontrolled to prevent deviation of synchronism by referring to theposition data.

Therefore, advanced synchronous operation is realized by preventingdeviation of synchronism relating to the position control.

Also in the drive control system of the invention, the present speeddata of each axis is shared by the synchronous axis, and it iscontrolled to prevent deviation of synchronism by referring to the speeddata.

Therefore, advanced synchronous operation is realized by preventingdeviation of synchronism relating to the speed control.

Also in the drive control system of the invention, each servo amplifierhas a regenerative resistor selectively set in conductive state by aregenerative transistor, the memory storing the regenerative load factordata of each axis, regenerative transistor state data, and bus voltagedata is shared by each servo amplifier, and it is controlled to turn onthe regenerative transistor of the servo amplifier smallest in theregenerative load factor data known from these data.

Therefore, the regenerative energy is consumed by the regenerativeresistor of the servo amplifier smallest in the regenerative load factordata, so that concentration of regenerative load can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an outline of a first embodiment ofdrive control system of the invention;

FIG. 2 is an explanatory diagram showing the content of shared memory inthe drive control system of the invention;

FIGS. 3(a) to (d) are explanatory diagrams showing communication packetsused in the drive control system of the invention;

FIG. 4 is a timing chart showing communication timing in the drivecontrol system of the invention;

FIG. 5 is an explanatory diagram showing conceptually the communicationoperation in the drive control system of the invention;

FIG. 6 is a block diagram showing an internal structure of serialcommunication interface used in the drive control system of theinvention;

FIG. 7 is an explanatory diagram showing the operation of the drivecontrol system of the invention;

FIG. 8 is a block diagram showing an outline of a second embodiment ofdrive control system of the invention;

FIG. 9 is an explanatory diagram showing the flow of data of inputsignal in the drive control system of the invention;

FIG. 10 is an explanatory diagram showing the flow of data of outputsignal in the drive control system of the invention;

FIG. 11 is an explanatory diagram showing the flow of data of analogspeed command in the drive control system of the invention;

FIG. 12 is an explanatory diagram showing the flow of data of speedcommand in the drive control system of the invention;

FIGS. 13(a) and (b) are explanatory diagrams showing address map ofshared memory and operation example of control unit of each axis in thedrive control system of the invention;

FIG. 14 is a block diagram showing outline of drive control system ofthe invention;

FIG. 15 is a block diagram showing an outline of a third embodiment ofdrive control system of the invention;

FIG. 16 is a block diagram showing a prior art of drive control system;

FIG. 17 is a block diagram showing an internal structure of serialcommunication interface in the conventional drive control system;

FIG. 18 is a timing chart showing communication timing in theconventional drive control system;

FIG. 19 is a format diagram of communication data in the conventionaldrive control system;

FIGS. 20(a) and (b) are timing charts showing reception data of outputdata and motor start processing in the conventional drive controlsystem;

FIG. 21 is a block diagram showing other prior art of drive controlsystem; and

FIG. 22 to FIG. 24 are block diagrams showing wiring examples of signallines in conventional drive control system.

BEST MODE FOR CARRYING OUT THE INVENTION

The invention is more specifically described below while referring tothe accompanying drawings.

FIG. 1 shows an outline of a first embodiment of drive control system ofthe invention. This drive control system comprises one control unit(master) 10, a plurality of servo amplifiers (slaves) 20 with CPU, and aplurality of remote input and output units 30, and all these devices areconnected by communication wires 50 to communicate in both ways andexist on a same communication system.

The control unit 10 includes a CPU (M/CPU) 11, and one serialcommunication interface 12 shared between the servo amplifiers 20 andremote input and output units 30, and the serial communication interface12 incorporates a communication memory 12 a in channel 1, acommunication memory 12 b in channel 2, a communication memory 12 c inchannel 3, an allout communication memory 12 d, and a designated numbercommunication memory 12 e.

Each servo amplifier 20 includes a CPU (S/CPU) 21, a motor drive circuit(M/D) 22, and a serial communication interface 23 for communication withthe control unit 10, and a servo motor 40 is connected thereto. Theservo motor 40 is provided with a rotary encoder, and returns a feedbacksignal to the motor drive circuit 22.

In this embodiment, nine servo amplifiers 20 are divided in to threegroups of three amplifiers each, and the groups are assigned withchannels 1 to 3.

The serial communication interface 23 of the servo amplifiers 20belonging to channel 1 incorporates a communication memory 23 a inchannel 1, an allout communication memory 23 d, and a designated numbercommunication memory 23 e. The serial communication interface 23 of theservo amplifiers 20 belonging to channel 2 incorporates a communicationmemory 23 b in channel 2, an allout communication memory 23 d, and adesignated number communication memory 23 e. The serial communicationinterface 23 of the servo amplifiers 20 belonging to channel 3incorporates a communication memory 23 c in channel 3, an alloutcommunication memory 23 d, and a designated number communication memory23 e.

Each remote input and output unit 30 includes a digital input interface(DI) 31, a digital output interface (DO) 32, an analog input interface(AI) 33, an analog output interface (AO) 34, and a serial communicationinterface 35 for communication with the control unit 10. The serialcommunication interface 35 incorporates an allout communication memory35 a.

Communication memories in channels and allout communication memoriesincorporated in serial communication interfaces 12, 23, 35 of thedevices are shared memories as seen from the CPU 11 and 21. As shown inFIGS. 2(a) to (c), the contents of communication memories 12 a, 23 a inchannel 1 are composed of TS1, TS2, TS3, RS1, and RS2, and the databeing read out by the CPU 11 of the control unit 10 from thecommunication memory 12 a in channel 1 and the data being read out bythe CPU 21 of the servo amplifier 20 from the communication memory 23 ain channel 1 are identical, the contents of communication memories 12 b,23 b in channel 2 are composed of TS4, TS5, TS6, RS3, and RS4, and thedata being read out by the CPU 11 of the control unit 10 from thecommunication memory 12 b in channel 2 and the data being read out bythe CPU 21 of the servo amplifier 20 from the communication memory 23 bin channel 2 are identical, and the contents of communication memories12 c, 23 c in channel 3 are composed of TS7, TS8, TS9, and RS5, and thedata being read out by the CPU 11 of the control unit 10 from thecommunication memory 12 c in channel 3 and the data being read out bythe CPU 21 of the servo amplifier 20 from the communication memory 23 cin channel 3 are identical. Similarly, the contents of alloutcommunication memories 12 d, 23 d, 35 a of the control unit 10, servoamplifier 20, and remote input and output unit 30 are mutually identicaldata among all constituent devices of the control unit 10, servoamplifier 20, and remote input and output unit 30.

FIGS. 3(a) to (d) show types of communication packets used in the drivecontrol system of the invention, and FIG. 4 shows the communicationtiming. There are four types of communication packets as shown in FIGS.3(a) to (d), that is, synchronous packet, in-channel communicationpacket, allout communication packet, and designated destinationcommunication (designated number communication) packet, and each packethas a mode designating unit and an sender number.

The synchronous packet shown in FIG. 3(a) is transmitted from thecontrol unit 10 to all constituent devices in batch in synchronism withthe reference clock shown in FIG. 4 as shown in FIG. 5(a). Thesynchronous packet includes a synchronous code, and receiving it, theserial communication interfaces 23 and 35 generate a synchronous clockon the basis thereof. The communication by the synchronous packettransmits, aside from the synchronous code, also command control data toeach constituent device (position command, speed command, torquecommand, on/off command) at the same time.

FIG. 3(b) shows an example of in-channel communication packet, and thein-channel communication packet is composed of channel number, beginningaddress in channel, data length, data, and redundancy code, and thecommunication in channel is executed as shown in FIG. 5(b), in whichdata is mutually transferred between the servo amplifiers 20 belongingto channels 1 to 3, and the control unit 10, and shared memories areformed in the channel. The data to be transmitted by the communicationin channel includes feedback data of each axis. In the conceptualdiagram of communication shown in FIG. 5(b), the sender is shown todesignate the destination, but actually the communication packet istransmitted to all constituent devices, and it is processed so as not toreceive the reception data at the receiving side by the mode data in thecommunication packet and the channel.

FIG. 3(c) shows an example of allout transmission packet, and the allouttransmission packet is composed of beginning address of address commonto all constituent devices, data length, data length to be changed,previous data before change, rewrite data, and redundancy code, and asshown in FIG. 5(c), the allout communication is transmitted from thesender to all constituent devices, and receiving this communicationmode, each constituent device rewrites the designated address by thedesignated data length. The data to be transmitted by the alloutcommunication includes I/O data and others.

FIG. 3(d) shows an example of designated destination communicationpacket, and the designated destination communication packet is composedof destination number, beginning address of destination, data length,data, and redundancy code, and as shown in FIG. 5(d), the designateddestination communication is done from the sender to the constituentdevice at the destination so as to transfer data between two arbitraryconstituent devices. The data is composed of communication packetcomprising conventional low speed data for the portion of a specificperiod, and parameter, program and other data are transmitted.

FIG. 6 shows an internal structure of serial communication interface 12provided in the control unit 10. The communication memory 12 a inchannel 1, communication memory 12 b in channel 2, communication memory12 c in channel 3, allout communication memory 12 d, and designatednumber communication memory 12 e incorporated in the serialcommunication interface 12 are composed of dual port RAMs, and areconnected to an external address bus 61 and an external data bus 62 atone side. The CPU 11 writes data from an external bus interface 63 intothe memory.

The serial communication interface 12 comprises a transmission-receptioncontroller 64, a reception register 65, a reception buffer 66, a modedetector 67 for detecting the mode from the mode data in thecommunication packet, a channel detector 68 for detecting the channeldesignated value in the communication packet, a beginning addressdetector 69, a data length detection data separator 70, a communicationfailure detector 71 for detecting communication abnormality from theredundancy code added to the communication packet, a synchronous clockgenerator 72, a channel selector 73 for judging whether or not to writereception data into the memory by collating the channel designated valueand the received channel designated value, and prohibiting writing ofdata of other than designated channel, a reception address counter 74,address decoders 75 a, 75 b, 75 c for each channel, an alloutcommunication address decoder 76, a previous data comparator 77, andreception control register setting unit 78 for storing the channeldesignated value set by parameter. The previous data comparator 77compares the received previous data and the present data in the alloutcommunication memory 12 d, and the data in the allout communicationmemory 12 d is written if matched, and writing into the alloutcommunication memory 12 d is prohibited if not matched.

The serial communication interface 12 further comprises a transmissioncontrol register setting unit 79, a transmission address counter 80, atransmission packet generator 81, a transmission buffer 82, atransmission waiting timer 83, and a transmission register 84. Thereception packet generator 81 includes a mode provider 81 a, a channelprovider 81 b, an address provider 81 c, a data length provider 81 d,and a redundancy code provider 81 e.

The transmission packet generator 81 can add the redundancy code inevery data quantity suited to the size of the buffer of transmission andreception, and at the reception side, in the communication failuredetector 71, communication failure is detected by the redundancy code inevery data quantity suited to the size of the buffer of transmission andreception, and if abnormal, writing into the memory is stopped, and ifthe communication packet quantity is less than the buffer size,communication failure is detected depending on the data length in thecommunication packet, and if abnormal, writing into the memory can bestopped.

The transmission control register setting unit 79 sets the transmissionwaiting time individually in each constituent device, shortens thewaiting time of the packet following the synchronous packet according tothe priority order, and starts reception when a constituent device highin priority order starts transmission within the waiting time, or startstransmission when other constituent device does not start transmissionafter a specified waiting time.

The serial communication interface 23 of the servo amplifier 20 iscomposed almost same as the serial communication interface 12 of thecontrol unit 10, except that it has as many in-channel communicationmemories as the number of channels connected and also possesses asynchronous clock generator 72.

In such serial communication interfaces 12, 23, the reception data isput into the reception buffer 66 through the reception register 65. Themode detector 67 selects the type of communication packet on the basisof the beginning data of the reception buffer 66.

Mode 0 means a synchronous packet, and the synchronous clock generator72 generates a clock synchronized with the synchronous code.

The channel detector 68 detects the channel from the reception data, anddepending on the channel set value stored in the reception controlregister setting unit 78, the channel selector 73 judges whether or notto write the received channel into the memory, and starts up thepertinent channel address decoders 75 a to 75 c when receiving.

The beginning address detector 69 detects the beginning address from thereception data, sets in the reception address counter 74, counts upsequentially by the portion of the data length detected in the datalength detection data separator 70, and stores the data separated in thedata length detection data separator 70 into the in-channelcommunication memories 12 a to 12 c designated in the channel addressdecoders 75 a to 75 c.

The communication failure detector 71 compares the redundancy code inthe reception data and the redundancy code generated from the receptiondata, and when matched, it is permitted to write the reception data inthe in-channel communication memories 12 a to 12 c, but if theredundancy codes are not matched, writing is prohibited to preventbreakdown of the in-channel communication memories.

When mode 1 is detected by the mode detector 67, the reception data isan in-channel communication packet, and the reception operation is sameas in mode 0 except that there is no effect on the synchronous clockgenerator 72.

When mode 2 is detected by the mode detector 67, the reception data isan allout communication packet, and the detected value of the beginningaddress detector 69 is written into the allout communication addressdecoder 76, and the previously received data the data stored at theaddress designated by the allout communication address decoder 76 arecompared in the previous data comparator 77, and the received rewritedata is written into the allout communication memory 12 d if matched,and received data is discarded if not matched.

When mode 3 is detected by the mode detector 39, the reception data is adesignated destination communication packet, and if the destination isthe receiving station, the reception data is stored in the designatednumber communication memory 12 e.

The transmission function is explained. The transmission function iscontrolled by the set value set in the transmission control registersetting unit 79, and when mode 0 is set, in synchronism with thesynchronous clock, channel address decoders 75 a to 75 c of the channelsdesignated by the channel set value are started, and by the instructionof the transmission address counter 80 storing the address set value,the values of the in-channel communication memories 12 a to 12 c areread out, and after adding the mode, channel, address, data length, andredundancy code by the transmission packet generator 81, thetransmission packets are sent into the transmission buffer 82, and aresequentially outputted from the transmission register 84.

In the case of transmission of modes 1, 2, 3, after completion ofreception of mode 0, waiting for the transmission waiting time set valueset in the transmission control register setting unit 79 by thetransmission waiting timer 83, if there is no reception data within thewaiting time, transmission control of the transmission-receptioncontroller 64 is started, and the data of the transmission buffer 82 isoutputted from the transmission register 84. Generation of transmissiondata is same as in the case of mode 0.

FIG. 7 is a diagram explaining the operation of the reception function,in which channel 1 is set, for example, in the reception controlregister setting unit 78.

First, receiving the in-channel communication packet, channeldesignation 1 is read from the reception data. The channel designatedvalue herein coincides with the channel set value of the receptioncontrol register setting unit 78, and after confirming there is nocommunication failure, writing into the memory is permitted, andspecified data length is written into the designated address. Receptiondata includes channel designation 2, but it is different from thechannel set value of the reception control register setting unit 78, andhence its writing is prohibited.

Successively, when the allout communication packet 1 and alloutcommunication packet 2 are consecutive, and rewrite request occurs at asame address, the operation is as follows. The data is read from thedesignated shared memory address of the allout communication packet 1,and is compared with the previously received data. When matched, rewritedata is stored in the designated address, and processing is completed.

Next, receiving the allout communication packet 2, when the same addressis designated, since the data has been already written, the result ofcomparison is not matched. Accordingly, writing is not permitted, andreceived data is discarded. As a result, the data in the previouslyreceived allout communication packet 1 is protected.

In the foregoing embodiment, there is only one reception controlregister setting unit 78, but by using the plurality of receptioncontrol register setting units 78, the number of channels that can bereceived simultaneously can be increased. Similarly, by using theplurality of transmission control register setting units 79, theplurality of modes can be transmitted sequentially, or by setting aplurality of channels, addresses or data length in the transmissioncontrol register setting unit 79, the plurality of data regions of theplurality of channels can be transmitted simultaneously to the sametransmission packet.

FIG. 8 shows a second embodiment of drive control system of theinvention. This drive control system has three servo amplifiers 100 forfirst axis, second axis, and third axis connected at the same level soas to communicate in two ways by communication wires 200, and exist on asame communication system.

Three servo amplifiers 100 for first axis, second axis, and third axisare identical in structure, each comprising a CPU 101, a motor drivecircuit 102, a digital input interface 103, a digital output interface104, an analog input interface (A/D converter) for speed command 105, apulse train input interface for position command 106, and a serialcommunication interface 107, and a servo motor 150 with rotary encoderis connected to each servo amplifier 100.

The serial communication interface 107 of the servo amplifier 100 foreach axis incorporates, as shared memories, an in-channel communicationmemory 107 a, an allout communication memory 107 b, and a designatednumber communication memory 107 c. The content of the in-channelcommunication memory 107 a in the servo amplifier 100 for each axis iscomposed of input data, output data, and pulse train commands for speedcommand and position command of each axis belonging to same channel.

The CPU 101 of the servo amplifier 100 for each axis writes the inputdata and pulse train commands for speed command and position commandentered in the digital input interface 103, analog input interface forspeed command 105, and pulse train interface 106 for position command ofthe own axis, into specified positions of the in-channel communicationmemory 107 a of the own axis, outputs the output data to the digitaloutput interface 104, and also writes into the specified position of thein-channel communication memory 107 a of the own axis.

When the input data, output data, and pulse train commands for speedcommand and position command are written into the in-channelcommunication memory 107 a, and the data contents are updated, theserial communication interface 107 transmits the new contents to theservo amplifier 100 for other axis belonging to the same channel. Whenthe servo amplifier 100 for other axis receives the updated data in theserial communication interface 107, the serial communication interface107 writes the updated data into the specified position of thein-channel communication memory 107 a.

As a result, in each axis, the data being red out from the in-channelcommunication memory 107 a is identical.

In the drive control system having such configuration, same as in theprior art shown in FIGS. 21(a) to (c), wiring of signal wires is asshown in FIG. 9 and FIG. 10 when assigning input signals of functions 1to 8 for all of first axis to third axis, output data of functions 11 to18 for first axis, output data of functions 21 to 24 for second axis,and output data of functions 31 and 32 for third axis.

In this case, input signals for functions 1 to 8 are wired only to theservo amplifier 100 for first axis, and wiring is not necessary in theservo amplifiers 100 for second axis and third axis. Output signals forfunctions 11 to 15 are wired to the servo amplifier 100 for first axis,output signals for functions 16 to 18 and functions 21 and 22 are wiredto the servo amplifier 100 for second axis, and output signals forfunctions 23, 24, 31, and 32 are wired to the servo amplifier 100 forthird axis.

FIG. 9 shows the flow of data of input signals for functions 1 to 8. TheCPU 101 for first axis reads the content (input data for functions 1 to8) of the digital input interface 103, and writes into the in-channelcommunication memory 107 a of the own station. The data in thein-channel communication memory 107 a is automatically written into thein-channel communication memories 107 a for second axis and third axisthrough the serial communication interface 107. As a result, the CPU 101for second axis and third axis reads out the content of the in-channelcommunication memory 107 a of the own machine (own station), and it canbe used in the control of the own axis.

Thus, wiring of input signals for functions 1 to 8 for the servoamplifiers 100 for second axis and third axis can be omitted.

FIG. 10 shows the flow of data of output signals for functions 11 to 18,functions 21 to 24, and functions 31 and 32.

The CPU 101 for first axis writes contents of output signals offunctions 11 to 15 into the in-channel communication memory 107 a of theown station as data for output signal of first axis, and writes contentsof output signals of functions 16 to 18 into the in-channelcommunication memory 107 a of the own station as data for output signalof second axis. In consequence, the data at the address corresponding tothe data for first axis output signal in the in-channel communicationmemory 107 a is read out, and written into the digital output interface104 of first axis, and a signal is outputted. The data in the in-channelcommunication memory 107 a is automatically written into the in-channelcommunication memories 107 a for second axis and third axis through theserial communication interface 107.

The CPU 101 for second axis writes contents of output signals offunctions 21 and 22 into the in-channel communication memory 107 a ofthe own station as data for output signal of second axis, and writescontents of output signals of functions 23 and 24 into the in-channelcommunication memory 107 a of the own station as data for output signalof third axis. In consequence, the data at the address corresponding tothe data for second axis output signal in the in-channel communicationmemory 107 a is read out, and written into the digital output interface104 of second axis, and a signal is outputted. The data in thein-channel communication memory 107 a is automatically written into thein-channel communication memories 107 a for first axis and third axisthrough the serial communication interface 107.

The CPU 101 for third axis writes contents of output signals offunctions 31 and 32 into the in-channel communication memory 107 a ofthe own station as data for output signal of third axis, reads out thedata at the address corresponding to the data for third axis outputsignal, writes into the digital output interface 104 of third axis, andoutputs a signal. The data in the in-channel communication memory 107 ais automatically written into the in-channel communication memories 107a for first axis and second axis through the serial communicationinterface 107.

By such serial communication, from the viewpoint of the entire system,the digital output interfaces 104 of servo amplifiers 100 for the axescan be used comprehensively without border of axes, and part of outputsignal for first axis can be outputted from the digital output interface104 for second axis, or the output signal for second axis can beoutputted from the digital output interface 104 for third axis.

Since the interface for digital output can be distributed to each axis,the number of interfaces for digital output mounted on each axis can bedecreased. According to a similar concept, the interface for digitalinput can be distributed in each axis, and the number of interfaces fordigital input mounted on each axis can be also decreased.

Moreover, since the input interface can be re-distributed, if desired toconnect an input signal of function 9 additionally, it may be wired tothe servo amplifier 100 for second axis or third axis where an extrainput interface is available, and similarly when adding an outputfunction of function 19, it is realized by connecting to the servoamplifier 100 for third axis.

FIG. 11 shows wiring of signal wires of analog speed command. FIG. 11 isan example of operation of each axis by using a same analog speedcommand, in which only by wiring the signal wire of analog speed commandto the servo amplifier 100 for first axis from a speed command unit 300and an analog output interface 301, the CPU 101 for first axis reads outthe speed command data of the analog input interface for speed command105, and writes the data into the in-channel communication memory 107 a.The data in the in-channel communication memory 107 a is automaticallywritten into the in-channel communication memories 107 a for second axisand third axis through the serial communication interface 107. As aresult, the CPU 101 of each servo amplifier 100 for first axis to thirdaxis reads out the address of the analog speed command of first axiswritten in the in-channel communication memory 107 a, and uses it inmotor control, so that synchronous operation of the first axis to thirdaxis is realized.

Besides, by preliminarily setting the shared memories as shown in FIG.13, the present speed data of each axis can be shared by thesynchronized three axes, so that deviation in synchronism can beprevented.

As mentioned above, by using shared memories among axes, the number ofwiring connections is decreased in the case of synchronous operation byusing analog speed command, and deviation in synchronism is prevented,and an advanced synchronous operation is realized.

FIG. 12 shows wiring of signal wires of position command (pulse traincommand). FIG. 12 is an example of operation of each axis by using asame pulse train command, in which only by wiring the signal wire ofpulse train command to the servo amplifier 100 for first axis from aposition command unit 310 and a pulse generator 311, the CPU 101 forfirst axis reads out the position command data of the pulse train inputinterface for position command 106, and writes the data into thein-channel communication memory 107 a. The data in the in-channelcommunication memory 107 a is automatically written into the in-channelcommunication memories 107 a for second axis and third axis through theserial communication interface 107.

As a result, the CPU 101 of each servo amplifier 100 for first axis tothird axis reads out the address of the position command of first axiswritten in the in-channel communication memory 107 a, and uses it inmotor control, so that synchronous operation of the first axis to thirdaxis is realized. Besides, by preliminarily setting the shared memoriesas shown in FIG. 13, the present position data of each axis can beshared by the synchronized three axes, so that deviation in synchronismcan be prevented.

Various examples of use of shared memories held by the servo amplifiers100 for axes are explained by referring to FIGS. 13(a) and (b). FIG.13(a) shows an example of address map of shared memories, and FIG. 13(b)shows an example of operation of control unit of each axis.

The shared memories hold the mapping of data on each axis, including notonly position command data, speed command data, torque command data,present position data, and present speed data, but also controlinformation in each servo amplifier such as bus voltage data,regenerative load factor data, effective load factor data, and statusdata. Further, digital input signal data, digital output signal data,analog input data, and analog output data of input and output units arealso disposed on the shared memories.

In example 1 of use of shared memory, a case of using in synchronousoperation of first axis and second axis is explained. The enteredcommand of pulse train input interface of first axis is always updatedas the data at the address of the first axis pulse train input data 1,and the first axis and second axis control the motor by using the dataas position command. On the second axis, the present position data ofthe first axis is always monitored, and if the first axis fails tofollow up the position command of the first axis pulse train input data1 due to some cause, by controlling so as to operate according to thepresent position data of the first axis, deviation in synchronism can beprevented.

In example 2 of use of shared memory, a fourth axis is a servo amplifierincorporating a position command generator for executing positioncontrol by generating a position command alone, and a case of causingthe third axis to follow up the fourth axis is explained. The fourthaxis generates a position command in the position command generator, andperiodically writes into the address of the fourth axis position commanddata of the shared memory. The third axis executes position control byusing this position command data, so that the third axis and fourth axisare operated simultaneously. In such control, hitherto, the fourth axismust have a function for issuing a pulse train command, and the pulsetrain command is accompanied by time delay for the processing period foroperation of pulse output function, but by using the shared memory, suchtime delay does not occur.

In example 3 of use of shared memory, sharing of bus voltage of firstaxis to fourth axis is explained. Usually, as shown in FIG. 14, theservo amplifier 100 has a diode 110, a capacitor 111, and an inverter112 as the power control unit. When a servo motor 150 slows down, acounter electromotive force (regenerative energy) is generated, and thecapacitor 111 is charged, and the bus voltage climbs up. The CPU 101monitors the bus voltage through a bus voltage detecting circuit 113,and turns on a regenerative transistor 115 through a regenerativetransistor control circuit 114 so as not to exceed the withstand voltageof the capacitor 111, and the bus voltage is lowered by consumingregenerative energy by a regenerative resistor 116.

The regenerative resistor 116 is designed to consume regenerative energyby heat exchange, and is accompanied by heat generation and temperaturerise, and therefore the CPU 101 manages the regenerative load factor andcontrols so that the regenerative resistor 116 may not generate heatover the specified temperature. Heat exchange by the regenerativeresistor 116 is basically loss of energy, and hence heat exchange by theregenerative resistor 116 must be kept as small as possible.

To decrease heat generation of the regenerative resistor 116 andsuppress energy loss, it is possible by increasing the capacity of thecapacitor 111, but increase of capacity of the capacitor 111 is limiteddue to the capacity of the servo amplifier.

Accordingly, as shown in FIG. 14, it is attempted to increase thecapacity of the capacitor on the whole by connecting buses 120 of theplurality of servo amplifiers 100. However, since each servo amplifier100 individually controls the regenerative transistor 115, theregenerative load may be concentrated on a certain servo amplifier 100due to detection error of bus voltage among devices or deviation inprocessing timing.

By adding regenerative load factor data, regenerative transistor statusdata, and bus voltage data of each axis to the shared memoryincorporated in the serial communication interface 107 of each servoamplifier 100, the servo amplifier 100 of each axis detects the entireregenerative load factor, and by turning on the regenerative transistor115 of the servo amplifier 100 smallest in the regenerative load factordata, and concentration of regenerative load is prevented, and theeffect of the capacitor capacity by connection of bus voltage of theplurality of servo amplifiers is obtained, thereby decreasing heatgeneration of the regenerative resistor 116 and suppressing energy loss.

FIG. 15 shows a third embodiment of drive control system of theinvention. In this drive control system, three servo amplifiers 400 forfirst axis, second axis, and third axis, and input and output units 410are connected so as to communicate in two ways by means of communicationwires 200, and exist on a same communication system.

Three servo amplifiers 400 for first axis, second axis, and third axisare identical in structure, each comprising a CPU 401, a motor drivecircuit 402, and a serial communication interface 403, and a servo motorwith rotary encoder (not shown) is connected to each servo amplifier400.

The serial communication interface 403 of the servo amplifier 400 foreach axis incorporates, as shared memories, an in-channel communicationmemory 403 a, an allout communication memory 403 b, and a designatednumber communication memory 403 c. The content of the in-channelcommunication memory 403 a in the servo amplifier 400 for each axis iscomposed of input data, output data, and pulse train commands for speedcommand and position command of each axis belonging to same channel.

The input and output unit 410 includes a CPU (RIO.CPU) 411, a digitalinput interface 413, a digital output interface 414, an analog inputinterface for speed command 415, and a pulse train interface forposition command 416, and a serial communication interface 417.

The serial communication interface 417 of the input and output unit 410incorporates, as shared memories, an in-channel communication memory 417a, an allout communication memory 417 b, and a designated numbercommunication memory 417 c, same as the serial communication interface403 of the servo amplifier 400. The content of the in-channelcommunication memory 417 a is same as that of the in-channelcommunication memory 403 a, being composed of input data, output data,and pulse train commands for speed command and position command of eachaxis belonging to a same channel.

In this drive control system, all of input signal wire, output signalwire, analog speed command signal wire and pulse train command signalwire are connected to the digital input interface 413, digital outputinterface 414, analog input interface for speed command 415, and pulsetrain interface for position command 416 of the input and output unit410.

The CPU 411 of the input and output unit 410 writes the input data andpulse train commands for speed command and position command entered inthe digital input interface 413, analog input interface for speedcommand 415, and pulse train interface for position command 416, inspecified positions of the in-channel communication memory 417 a. As theinput data and pulse train commands for speed command and positioncommand are entered in the in-channel communication memory 417 a, andthe data contents are updated, the serial communication interface 417transmits them to the servo amplifier 400 belonging to the same channel.When the servo amplifier 400 receives the updated data in the serialcommunication interface 403, the serial communication interface 403writes the updated data into specified position of the in-channelcommunication memory 403 a of the own axis.

The CPU 401 of the servo amplifier 400 for each axis writes the outputdata into specified position of the in-channel communication memory 407a of the own axis, and this output data is written into the in-channelcommunication memory 403 a of the servo amplifier 400 of other stationand in-channel communication memory 403 a of the input and output unit410 by means of the serial communication interface 403. The input andoutput unit 410 outputs the output data written in the in-channelcommunication memory 403 a from the digital output interface 414.

In this embodiment, it is enough to connect the signal wires to theinput and output unit 410, and wiring is easier, and the same effectsand actions as in the second embodiment are obtained.

INDUSTRIAL APPLICABILITY

The invention is used as the drive control system for speed control andposition control by a plurality of servo motors or spindle motors inmachine tools and other industrial machines.

What is claimed is:
 1. A drive control system having constituent devicesconnected so as to communicate with each other, wherein a memory isprovided in each of the constituent devices, the constituent devices ofthe drive control system are synchronized with each other, acommunication unit is provided for transferring memory data betweenselected constituent devices of the drive control system, and at leastone of said memory that is provided in each of the constituent devicesof the drive control system, is shared simultaneously between saidselected constituent devices of the drive control system.
 2. A drivecontrol system having constituent devices connected so as to communicatewith each other, wherein a memory is provided in each of the constituentdevices, the constituent devices are synchronized with each other, acommunication unit is provided for transferring memory data betweenselected constitutent devices, and at least one of said memory that isprovided in each of the constituent devices, is shared simultaneouslybetween said selected constituent devices, wherein communication datacomprises a synchronous packet used for generating a clock transmittedin a specific method period so that all constituent devices aresynchronized therewith, an in-channel communication packet used forsharing said at least one of said memory within a same group, an alloutcommunication packet used for sharing said at least one of said memorybetween all constituent devices, and a designated destinationcommunication packet for communicating by designating the destination oftransmission of a parameter.
 3. The drive control system of claim 2,comprising a control unit and a servo amplifier, wherein each of thecontrol unit and servo amplifier has a communication memory in eachchannel, a transmitter transmits the in-channel communication packetincluding a channel designated value, an address, a transmission datalength and data to all constituent devices, and a receiver judgesapproval or rejection of reception by collating the channel designatedvalue included in the communication packet and a channel set value setin a parameter in each servo amplifier, and writes the data of thecommunication packet of the collated channel in the communicationmemory.
 4. A drive control system having constituent devices connectedso as to communicate with each other, wherein a memory is provided ineach of the constituent devices, the constituent devices aresynchronized with each other, a communication unit is provided fortransferring memory data between selected constituent devices, and atleast one of said memory that is provided in each of the constituentdevices, is shared simultaneously between said selected constituentdevices, said drive control system comprising a control unit, a servoamplifier, and an input and output unit, each having alloutcommunication memories, wherein a transmitter transmits an alloutcommunication packet including a sender number, an address, atransmission data length, a variable data length, previous data, andrewrite data to all constituent devices, a receiver compares thereceived previous data and the data in the present allout communicationmemory, the data in the allout communication memory is rewritten, ifmatched, and writing into the allout communication memory is stopped, ifnot matched.
 5. The drive control system of claim 2, wherein atransmitter adds a redundancy code to the communication packet in everyquantity of data that is based on the size of a buffer, and a receiverdetects communication failure according to the redundancy code in everyquantity of data that is based on the size of the buffer, and writinginto said at least one of said memory is stopped, if abnormal.
 6. Thedrive control system of claim 2, wherein a waiting time of eachcommunication following the synchronous packet is shortened depending ona priority order, and when a constituent device high in priority orderstarts transmission within the waiting time, reception is started, andafter completion of reception, if another constituent device does notstart transmission after lapse of a specified waiting time, transmissionis started.
 7. A drive control system having constituent devicesconnected so as to communicate with each other, wherein a memory isprovided in each of the constituent devices, the constituent devices aresynchronized with each other, a communication unit is provided fortransferring memory data between selected constituent devices, and atleast one of said memory that is provided in each of the constituentdevices, is shared simultaneously between said selected constituentdevices, wherein said at least one of said memory stores input data,output data, position command, and speed command, is shared by theconstituent devices.
 8. The drive control system of claim 7, whereinpresent position data of each axis is shared by a synchronous axis, andthe synchronous axis is controlled to prevent deviation of synchronismby referring to the position data.
 9. The drive control system of claim7, wherein present speed data of each axis is shared by a synchronousaxis, and the synchronous axis is controlled to prevent deviation ofsynchronism by referring to the speed data.
 10. The drive control systemof claim 3, wherein the servo amplifier has a regenerative resistorselectively set in conductive state by a regenerative transistor, saidat least one of said memory storing regenerative load factor data ofeach axis, regenerative transistor state data, and bus voltage data thatis shared by the servo amplifier, and the bus voltage data is controlledto turn on the regenerative transistor of the servo amplifier smallestin the regenerative load factor data known from these data.
 11. Thedrive control system of claim 1, wherein said constituent devicescomprise at least one of a control unit, a servo amplifier, a spindleamplifier, and an input/output unit.
 12. A drive control system having aplurality of constituent devices connected so as to communicate witheach other, wherein a memory and a communication unit are provided ineach of the constituent devices of the drive control system, theconstituent devices of the drive control system are synchronized witheach other, the communication unit transfers memory data between atleast two of the constituent devices of the drive control system so thatidentical memory data are simultaneously stored in the memory in said atleast two of the constituent devices of the drive control system,thereby enabling the memory provided in said at least two of theconstituent devices of the drive control system to be used as sharedmemories.